Huawei announced a new semiconductor design approach on Monday that it says will substantially improve smartphone chip performance, presenting the technology at a global industry conference as the company works around U.S. restrictions on advanced manufacturing tools.
At the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai on May 25, 2026, He Tingbo, president of Huawei’s semiconductor business unit, delivered a keynote titled “New Semiconductor Path in Practice.”
She introduced what the company calls the Tau Scaling Law, a design framework Huawei says replaces the industry’s long-dominant reliance on shrinking transistors.
The Tau Scaling Law proposes replacing geometric scaling, the basis of Moore’s Law, with time-based scaling as a guiding principle for how semiconductors and electronic systems develop.
In practical terms, it shifts focus from transistor size toward reducing how long signals take to travel inside a chip.
How LogicFolding Changes the Kirin Architecture
Alongside the Tau Scaling Law, Huawei unveiled a chip design approach called LogicFolding.
The company said the architecture would shorten wiring inside chips and considerably improve performance.
Its upcoming Kirin processors, scheduled to launch in fall 2026, will be the first commercial chips to use it.
Compared with a conventional system-on-chip design, the LogicFolding architecture is claimed to deliver a 53.5% increase in transistor density, reaching up to 238 million transistors per square millimeter.
The company also claims a 40% improvement in performance-core power efficiency and a maximum clock frequency increase of 12.7%, reaching up to 3.1 GHz. Huawei did not provide independent verification for any of these figures.
He Tingbo said the company spent six years building domestic semiconductor capabilities, including electronic design automation tools and chip design methods.
“I used to think it may take us 10 years, but six years we are here,” she said.
She added a firm public milestone: “Before winter 2026, we will bring the surprise, a big leap ahead.”
What the Announcement Signals Beyond Smartphones
Huawei reported that it has already designed and mass-produced 381 chips over the past six years based on the Tau Scaling Law, spanning smartphones and AI computing.
The broader context is significant. Demand for Huawei’s Ascend AI chips has risen in China this year as domestic tech companies seek alternatives to Nvidia, whose most advanced processors are restricted from sale to China.
Nvidia CEO Jensen Huang said earlier this month that the company had “largely conceded” China’s AI chip market to Huawei.
SMIC shares rose 7.6% on May 25 after Huawei’s LogicFolding announcement. SMIC is China’s largest contract chipmaker and the manufacturer of Huawei’s current Kirin chips.
Analysts Flag Questions on Scale and Manufacturing
Not everyone accepts the claims at face value. Paul Triolo, head of technology, Asia and Americas at DGA Group, offered a pointed qualification.
“A stacked or folded design can produce effective density gains, but it does not mean Huawei has solved the full process, yield, power, thermal, and device-performance problems associated with true 1.4 nm-class manufacturing,” he said.
Neil Shah, vice president of research at Counterpoint Research, echoed that caution. “This parallel semiconductor path is still unproven at scale.
This approach can introduce tough thermal constraints and packaging complexities that can hit manufacturing yields,” Shah said.
He Hui, director of semiconductor research at Omdia, took a more measured view. “What Huawei is proposing is a shift from traditional node-driven scaling to system-level efficiency scaling.
Shortening interconnect, lowering latency, and improving data movement inside the chip is a credible way to extract more performance when leading-edge lithography is constrained,” she said.
Analysts broadly say China remains behind global leaders in the most advanced process technology, even as Huawei and its Chinese partners show progress.
What Comes Next
2031: Huawei’s stated target for high-end chips to reach transistor density equivalent to 1.4-nanometer processes, per the company’s roadmap. No independent timeline verification has been provided.
